ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 90
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ST10F272M-4Q3
Manufacturer Part Number
ST10F272M-4Q3
Description
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST10F272M-4Q3.pdf
(175 pages)
- Current page: 90 of 175
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System reset
20.5
90/176
Refer to the next Figures
and
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to next Figures
29
Figure 25. SW / WDT unidirectional RESET (EA = 1)
for bidirectional.
29
for bidirectional.
RSTIN
P0[15:13]
P0[12:8]
P0[7:2]
P0[1:0]
IBUS-CS
(Internal)
FLARST
RST
RSTOUT
25
and
25
and
26
for unidirectional SW reset timing, and to Figures 27,
26
1024 TCL
for unidirectional SW reset timing, and to Figures 27,
not transparent
not transparent
not transparent
transparent
≤ 1ms
≤ 2 TCL
not t.
not t.
7 TCL
ST10F272M
28
and
28
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