ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 163
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ST10F272M-4Q3
Manufacturer Part Number
ST10F272M-4Q3
Description
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST10F272M-4Q3.pdf
(175 pages)
- Current page: 163 of 175
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ST10F272M
24.8.18
Table 72.
1. These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
more time for deactivating READY. 2t
CC CLKOUT cycle time
CC CLKOUT high time
CC CLKOUT low time
CC CLKOUT rise time
CC CLKOUT fall time
CC CLKOUT rising edge to ALE falling edge
SR
SR
SR Asynchronous READY low time
SR Asynchronous READY setup time
SR Asynchronous READY hold time
SR
Synchronous READY setup time to
CLKOUT
Synchronous READY hold time after
CLKOUT
Asynchronous READY hold time after RD,
WR high (Demultiplexed Bus)
CLKOUT and READY
V
CLKOUT and READY timings
DD
= 5V ± 10%, V
Parameter
SS
A
and t
= 0V, T
(2)
(1)
C
(1)
refer to the next following bus cycle, t
A
= -40 to + 125°C, CL = 50pF
-2 + t
Min
25
10
17
35
17
f
9
–
–
2
2
0
TCL = 12.5ns
CPU
A
= 40 MHz
2t
A
8 + t
Max
+ t
25
–
–
4
4
–
–
–
–
–
C
F
A
+ t
refers to the current bus cycle.
F
2TCL + 10
1/2 TCL = 1 to 40 MHz
TCL - 3.5
TCL - 2.5
Electrical characteristics
Variable CPU clock
-2 + t
2TCL
Min
17
17
–
–
2
2
0
A
2t
A
2TCL
8 + t
Max
+ t
–
–
4
4
–
–
–
–
–
C
A
+ t
163/176
F
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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