MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 18

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H28
4.1.1.2 Register Data Port (RDP)
4.1.2 Control and Status Register Definition
4.1.2.1 Control and Status Register 0 (CSR0)
RAP<3:1> = 0
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BIT
BIT
15
14
13
12
CSR DATA
1
5
1
5
P
T
D
M
D
PTDMD
NAME
NAME
STOP
DTX
DRX
1
4
1
4
S
T
O
P
1
3
1
3
D
T
X
Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from
RDP reads the data from the CSR selected in RAP.
Transmit Demand for Priority DLCIs. Setting this bit to 1 causes the MK50H28 to jump to
Priority DLCI Block (PDB). This bit is cleared by the MK50H28 after servicing all active
entries in the PDB. (Note: See section 4.2.9 for more details.)
STOP, when set, indicates that MK50H28 is operating in the STOPPED Phase of
operation. All external activity is disabled and internal logic is reset. MK50H28 remains
inactive except for primitive processing until a START primitive is issued. STOP IS READ
ONLY and set by Bus RESET or a STOP primitive. Writing to this bit has no effect.
Disable Transmitter. Prevents the MK50H28 from further access to the Transmitter
Descriptor Rings. No transmissions are attempted after finishing transmission of any
frame in transmission at the time of DTX being set. Even LMI frames normally generated
automatically will not be transmitted if DTX=1. TXON acknowledges changes to DTX,
see below. DTX is READ/WRITE.
Disable the Receiver prevents the MK50H28 from further access to the Receiver
Descriptor Rings. No received frames are accepted after finishing reception of any frame
in reception at the time of DRX being set. Setting DRX will put the MK50H28 in the
LOCAL BUSY Phase. RXON acknowledges changes to DRX, see description of RXON.
DRX is READ/WRITE.
1
2
1
2
D
R
X
1
1
1
1
T
X
O
N
1
0
1
0
R
X
O
N
CSR
0
9
0
9
I
N
E
A
0
8
0
8
I
N
T
R
0
7
0
7
M
E
R
R
DATA
DESCRIPTION
DESCRIPTION
0
6
0
6
M
I
S
S
0
5
0
5
R
O
R
0
4
0
4
T
U
R
0
3
0
3
P
I
N
T
0
2
0
2
T
I
N
T
0
1
0
1
R
I
N
T
0
0
0
0
0