MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 27

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

4.2 Initialization / Priority DLCI Block
MK50H28 initialization includes the reading of the Initialization Block in the off-chip memory to obtain the
operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, the first
16 words of the Initialization block are read by the MK50H28. The remainder of the Initialization block
will be read as needed by the MK50H28. Memory at IADR+32 - IADR+38 should always be initialized
with 0’s prior to issuing the Init Primitive. Any changes to IADR+00 - IADR+31 after initialization require
that the device be stopped and Init primitive be issued again in order to take effect. It is not necessary
that the device be re-initialized after changes to bits in the CSRs (Control and Status Registers).
Figure 8: Initialization / Priority DLCI Block
BASE ADDRESS
HIGHER ADDR
Counter nN1/N391
Ntwk N393
RESERVED-Must be written with 0’s
Counter dN1 (Max Frame Length)
Counter nN1
(If EIBEN=1)
RESERVED
RESERVED
RESERVED
RESERVED
ERROR COUNTERS
Ntwk N392
Timer nT1 / T391
(256 Entries Maximum)
Timer nT2 / T392
CTADR <15:00>
TINTADR <23:16>
RINTADR <23:16>
and STATISTICS
PRIORITY DLCI
ALTADR <15:00>
SBA <15:00>
RESERVED
Timer TP
RESERVED
MODE
BLOCK
ALTADR <23:16>
TINTADR<23:16>
RINTADR<23:16>
User N393
CTADR <23:16>
SBA <15:00>
/ nN3
SCALER
User N392
/ nN2
IADR+00
IADR+02
IADR+04
IADR+06
IADR+08
IADR+10
IADR+12
IADR+14
IADR+16
IADR+18
IADR+20
IADR+22
IADR+24
IADR+28
IADR+40
IADR+42
IADR+44
IADR+32-38
IADR+89
IADR+96
IADR+XX
THRU
THRU
MK50H28
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