MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 39

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

4.3.1 Receive Message Descriptor Entry
4.3.1.1 Receive Message Descriptor 0 (RMD0) For Non-LMI Channel
4.3.1.2 Receive Message Descriptor 0 (RMD0) For LMI Channel
07:00
BIT
BIT
15
14
13
12
11
10
09
08
15
RBADR
OWNA
OWNA
1
5
O
W
N
A
NAME
NAME
FECN
BECN
FRER
EOR
ELF
1
5
O
W
N
A
C/R
DE
1
4
E
O
R
1
4
E
O
R
C/R
1
3
When this bit is a zero the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The chip clears the OWNA bit after filling the buffer
pointed to by the descriptor entry provided a valid frame has been received. The Host
sets the OWNA bit after emptying the buffer. Once the MK50H28 or the Host has
relinquished ownership of a buffer, it may not change any field in the four words that
comprise the descriptor entry.
End Of Ring. This bit is set by the host to indicate that this is the last descriptor in the
ring.
Command/Response Indication Bit. This bit equals the state of the C/R bit for the
received frame.
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. ELF is used for data chaining buffers and is set by the MK50H28. ELF=0
indicates that this buffer is one in a chain. When not chaining, ELF will always be one.
Forward Explicit Congestion Notification Bit. This bit equals the state of the FECN bit for
the received frame.
Backward Explicit Congestion Notification Bit. This bit equals the state of the BECN bit for
the received frame.
Discard Eligibility Bit. This bit equals the state of the DE bit for the received frame.
Frame in Error Bit. This bit is valid only if RBFRS is set in CTADR+12. This bit will be set
by the MK50H28 only if an aborted or a bad FCS frame is received.
The High Order 8 address bits of the buffer pointed to by this descriptor. This field is
written by the Host and unchanged by MK50H28.
1
3
When this bit is a zero, the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The chip clears the OWNA bit after filling the buffer
pointed to by the descriptor entry, provided a valid frame has been received. The Host
should set the OWNA bit after emptying the buffer. Once the MK50H28 or Host
relinquishes ownership of a buffer, it may not change any field in the descriptor entry.
0
1
2
E
L
F
1
2
E
L
F
1
1
F
E
C
N
1
1
Frame
Type
1
0
B
E
C
N
1
0
DE R
0
9
0
9
0
8
F
E
R
0
8
F
R
E
R
0
7
0
7
DESCRIPTION
DESCRIPTION
0
6
0
6
0
5
0
5
RBADR<23:16>
RBADR<23:16>
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
MK50H28
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