MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 48

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H28
4.4.5 Receiving LMI Frames
The following procedure should be performed to receive the LMI frames:
4.4.6 Link Congestion
4.4.7 Transmitting the LMI Frames (non-Auto LMI)
The following procedure should be performed to transmit the LMI frames:
4.4.8 Transparent Transmission of Frames from LMI Buffer
The following procedure should be performed to transmit the LMI frames:
4.4.9 Transmission of Frames From Higher Priority DLCI(s)
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1. Whenever a LMI frame is received the MK50H28 issues a PPRIM of 13. In response to that the
2. Except for the DLCI header field all of the data field will be placed in the receive buffer(s).
3. For LMI frames received, bits 9-11 in RMD0 of the receive descriptor will indicate the type of LMI
4. In Non-Auto-LMI mode of operation, LMI frames received on the LMI Channel (typically DLCI 0)
1. The host determines congestion on a link. One way it can do is through the congestion statistics
2. The host will set TXCONG and/or RXCONG for transmit and receive congestions.
3. If TXCONG is set the MK50H28 will not transmit any frames with DE=1 for that link.
4. If RXCONG is set any frames received with DE = 1 will be discarded. The frame discarded
5. When a channel comes out of congestion, the host should clear TXCONG, RXCONG and
1. The MK50H28 (user) sends the STATUS_ENQUIRY frame to the network using UPRIM = 10. A
2. The MK50H28 (network) sends the UPDATE_STATUS frame to the user using UPRIM of 12 with
3. The MK50H28 (network) will send the STATUS frame to the user when a UPRIM of 11 is issued.
1. Follow the steps outlined in Programming Procedure 4.4.3 for sending data from any DLCI.
1. Set the bit XTRAN=1 in the Context Table 0 entry (the LMI CT entry).
2. Issue the Send LMI primitive 14. (See UPRIM14 and XTRAN descriptions for more details).
1. Set up the Priority DLCI Block contiguous with the end of the Initialization Block.
2. Input appropriate index (indices) to the desired Context Table entry and set the ACTIVE bit.
3. Set the PTDMD bit in CSR0 (bit 15). See section 4.2.9 for more details.
host may look at the PPARM field to identify the frame type received
frame received. A setting of 000 indicates a received SVC frame or Transparent Mode frame.
will be written into the receive buffer as Transparent or SVC frames.
and counters in the CT.
counter in the CT will keep track of the frames with DE = 1 discarded during congestion. If this
still does not help congestion, the host can clear the RXRDY bit. Then all the frames received on
that link will be discarded. The MK50H28 will set RXMISS bit in the CT and will generate a
MISS interrupt if INEA = 1 in the CSR 0.
RXMISS bits in the CT.
UPRIM of 10 with UPARM of 0 should be issued by the user to request Full STATUS frame from
the network. For Sequence Numbers Exchange only a UPRIM of 10 with UPARM of 1 should
be issued by the user.
UPARM of 0. In order to transmit Optional Information Elements (MULTICAST_STATUS and
PVC_STATUS), the host should place this information in the LMI Transmit Buffer(s).
A UPRIM of 12 with UPARM of 0 causes the transmission of a Full STATUS frame. The Optional
Information Elements (PVC_STATUS and may be MULTICAST_STATUS) should be placed in
the LMI transmit buffer(s). A UPRIM of 12 with UPARM of 1 sends only the Sequence Number
information to the user.
NOTE: The host can use LMI Frame transmission provider primitive 12 to start nT1/T391 or
nT2/T392 timers.