MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 23

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

4.1.2.3 Control and Status Register 2 (CSR2)
RAP<3:1> = 2
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1>
= 3
07:00
15:00
BIT
BIT
15
14
13
12
11
10
09
08
DLCI1K
CYCLE
LMICH
1
5
NAME
EIBEN
TDMD
NAME
1
5
C
Y
C
L
E
TRAN
ANXD
IADR
IADR
0
1
4
1
4
E
I
B
E
N
1
3
1
3
D
L
C
I
1
K
Setting this bit selects a shorter DMA Cycle (5 vs 6 SYSCLK)
Extended Initialization Block Enable. Setting this bit causes the MK50H28
extended Initialization Block which uses all of IADR+08 as a 16-bit scaler and moves nN1
to the upper byte of IADR+40.
Setting this bit causes the chip to recognize the 8192 possible DLCIs.If this bit is cleared,
the chip will ignore all received frames with DLCI greater than 1023.
CHLMI Channel Select: Setting this bit to 0 causes frames received on DLCI 0 to be
treated as LMI frames.. Setting it to 1 causes frames received on DLCI 1023 to be treated
as LMI frames. NOTE: Regardless of the setting of this bit, only the first entry in the
Context Table table (CT0) will be used for transmission and reception of LMI
frames.
Should be set only if frames need to be transmitted without protocol processing from the
transmit buffers. With this bit set, the chip will not prepend an address field when
transmitting data from the buffers, but rather, the buffers should have both address and
data information for proper Frame Relay protocol.
Reserved. Must be written as zeroes.
Setting this bit enables operation in conformance with T1.617 Annex D specifications.
With ANXD=0, the MK50H28 operates in conformance with CCITTQ.933 Annex A.
Transmit Demand. Setting this bit causes the MK50H28 to ignore the TP (Transmit Poll
timer) and continuously poll all Context Table entries until TDMD is cleared by the host.
The high order 8 bits of the address of the first word in the Initialization Block. IADR must
be written by the Host prior to issuing an Init Request primitive.
The low order 16 bits of the address of the first word in the Initialization Block. Must be
written by the Host prior to issuing an Init Request primitive. The Initialization block must
begin on a word boundary.
1
2
1
2
L
M
I
C
H
1
1
1
1
T
R
A
N
1
0
IADR <15:00>
1
0
0
0
9
0
9
A
N
X
D
0
8
T
D
M
D
0
8
0
7
0
7
0
6
DESCRIPTION
DESCRIPTION
0
6
0
5
0
5
IADR<23:16>
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
to use an
MK50H28
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