MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 40

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H28
4.3.1.2 Receive Message Descriptor 0 (RMD0) For LMI Channel (Contimued)
4.3.1.3 Receive Message Descriptor 1 (RMD1)
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11:09
07:00
15:01
BIT
BIT
14
13
12
08
LMI Frame
Received
1
5
RBADR
RBADR
NAME
NAME
FRER
Type
EOR
ELF
0
1
4
1
3
End Of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.
Reserved. Must be written as zero.
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. ELF=0 indicates that this buffer is one in a chain. ELF=1 indicates the end of the
buffer chain. ELF is set by the MK50H28. When not chaining, ELF will always be one.
These bits define the type of frame received, as detailed in the following table:
Frame in Error Bit. This bit is valid only if RBFRS is set in CSR 2. This bit will be set by
the MK50H28 only if an aborted or a bad FCS frame is received.
The High Order 8 address bits of the buffer pointed to by this descriptor. This field is
written by the Host and unchanged by MK50H28.
The low order 16 address bits of the receive buffer pointed to by this descriptor.
RBADR is written by the Host CPU and unchanged by MK50H28. The receive buffers
must be word aligned.
1
2
Bit Encoding (MSB - LSB)
1
1
1
0
000
001
010
011
100
101
110
111
RBADR<15:00>
0
9
0
8
0
7
Frame Type
SVC Frame or Transparent Mode frame
Reserved
Full Status Enquiry frame
Status Enquiry frame (LIV only)
Asynchronous Status Frame
Update Status frame
Full Status frame
Status frame (LIV only)
DESCRIPTION
DESCRIPTION
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0