MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 43

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

4.3.2.3 Transmit Message Descriptor 1 (TMD1)
4.3.2.4 Transmit Message Descriptor 2 (TMD2)
11:09
11:09
07:00
15:00
15:00
BIT
BIT
BIT
08
Transmitted
LMI Frame
Type to be
TBADR
TBADR
NAME
TINTD
NAME
NAME
BCNT
1
5
1
5
0
1
4
1
4
These bits define the type of frame to be transmitted when transmission occurs due to
LMI polling (enabled by UPRIM 8 with UPARM=2 - see 4.1.2.2).
Reserved. Must be written as zero.
Transmit Interrupt Disable. If this bit is set, no transmit interrupt is generated when
ownership of this descriptor is released back to the host.
The High Order 8 address bits of the buffer pointed to by this descriptor.
This field is written by the Host and unchanged by MK50H28.
The Low Order 16 address bits of the buffer pointed to by this descriptor. TBADR is
written by the Host and unchanged by MK50H28. The least significant bit is zero since
the descriptor must be word aligned.
Buffer Byte Count is the usable lenght of the buffer pointed to by this descriptor
expressed in two’s complement. Thiis field is not used by the MK50H28.
1
3
1
3
Bit Encoding (MSB - LSB)
1
2
1
2
1
1
1
1
000
001
010
011
100
101
110
111
1
0
1
0
TBADR<15:00>
0
9
0
9
BCNT<15:00>
0
8
0
8
0
7
Frame Type
SVC Frame or Transparent Mode frame
Reserved
Full Status Enquiry frame
Status Enquiry frame (LIV only)
Asynchronous Status Frame
Update Status frame
Full Status frame
Status frame (LIV only)
0
7
DESCRIPTION
DESCRIPTION
DESCRIPTION
0
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
MK50H28
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