MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 33

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

The contents of each CT entry block are described below:
CT+02,+04
CT+06,+08
WORD
CT+00
CT+02
CT+10
CT+12
TXRDY (15) The host sets this bit only if the channel is ready to transmit. If this bit is not set, the
XTRAN (11) Transmit Transparent. Setting this bit causes frames to be transmitted transparently from
RTRAN (11) Receive Transparent. When RTRAN=1, received frames will be written into the
FECSEN (8) FCS Pass-Through Enable. Setting this bit allows the FCS or CRC to be stored in the
ENIDX (13)
RINTD (10)
RBFRS (9)
DLCI Field
RXCONG
TXCONG
EOCT (8)
TXMXFR
RXMISS
CURXD
IDXPTR
RXRDY
NAME
TDRA
(15:8)
(15:3)
(7:0)
(14)
(15)
(14)
(13)
MK50H28 will not transmit data for that channel.
The host sets this bit only if the channel is in congestion on the transmit path. If this bit is
set, frames with the DE bit set in TMD0 will be discarded and not transmitted. This is also
valid even if XTRAN=1. During normal transmission (i.e., no congestion), the host should
clear this bit.
Enable Index Pointer to next entry in CT. Setting this bit, causes the device to jump and
service the CT entry pointed to by the IDXPTR (CT+10) rather than servicing the next
sequential CT entry.
the corresponding TX Descriptor Ring and buffer without pre-pending any frame header.
This bit should typically be set for Transparent Mode operation.
End Of Context Table. Setting this bit indicates that this is the last entry in the CT. From
here the device will advance to the begining of the CT and service the first non-LMI entry.
Maximum Number of Frames to be consecutively transmitted. The device uses this value
to determine the maximum number of frames to be transmitted before advancing to the
next channel. This field is only used if the number of frames queued in the descriptor ring
are greater than TXMXFR. This field must contain the two’s complement number.
Specifies the current transmit descriptor in the ring (0 - 127 in the upper 7 bits). This field
should initially be written with zeroes.
Starting address (must begin on a word boundary) of the Transmit Ring for channel.
The MK50H28 can handle up to 4 octets of address field. For the LMI channel only, the
MK50H28 transmits the entire address field as specified in the CT. For all other active
channels, the explicit congestion bits (FECN, BECN, and DE) and the C/R bit are
modified by the corresponding bits in the Transmit Message Descriptor 0 (TMD0) and
should be written as 0.
During reception for all the non-LMI active channels, the explicit congestion bits and the
C/R bit will be written in the Receive Message Descriptor 0 (RMD0). For the LMI channel
these bits are ignored.
Index Pointer. The MK50H28 uses this field only when bit ENIDX is set. This field should
contain the Index Pointer to the next CT entry to be serviced. All 13 bits of this field will be
used as an index into the CT, regardless of the seting of DLCI1K in CSR2.
The host sets this bit only if the channel is ready to receive data. If the bit is not set, all
received frames will be discarded for the channel.
The host sets this bit only if the channel is experiencing congestion on the receive path.
When this bit is set the MK50H28 will discard only the received frames with Discard
Eligibility (DE) = 1 for that channel. A counter in the CT (see below for more information)
keeps track of received frames with DE = 1 that are discarded due to congestion. During
normal reception (i.e., no congestion) & Transparent Mode this bit should be cleared to 0.
This bit is set by the MK50H28 when during reception of a frame either the channel is not
ready (i.e., RXRDY = 0) or the receiver does not own a buffer (i.e., OWNA = 0. See 4.3.1
Receive Message Descriptor 0). Also if INEA = 1 in CSR 0, a MISS packet error interrupt
will be generated under the above conditions. During normal reception the host should
clear this bit. The address where the MISS occured can be determined by issuing a
Status Request primitive. For more information see under Status Buffer.
corresponding RX Descriptor Ring buffer without stripping any frame header, and FECN,
BECN & DE bits in RMD0 will not be updated. CT counters and statistics will still be
updated. This bit should be set for Transparent Mode Operation.
Receive Interrupt Disable. Setting this bit prevents the device from generating Receive
Interrupts (RINT) for this channel.
Receive Bad Frames. If set, the MK50H28 will receive both aborted and Bad FCS
frames. For such received frames the FRER bit in the RMD0 will be set.
buffer along with the frame data.
DESCRIPTION
MK50H28
33/64