MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 42

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H28
4.3.2.2 Transmit Message Descriptor 0 (TMD0) For LMI Channel
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BIT
BIT
15
14
13
12
11
10
09
08
15
14
13
12
1
5
O
W
N
A
TBADR
OWNA
OWNA
NAME
TINTD
NAME
FECN
BECN
EOR
EOR
ELF
ELF
C/R
DE
0
1
4
E
O
R
1
3
0
When this bit is a zero, the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The host sets the OWNA bit after filling the buffer
pointed to by the descriptor entry. The MK50H28 releases the descriptor after
transmitting the buffer. After the MK50H28 or the Host has relinquished ownership of a
buffer, it may not change any field in the four words that comprise the descriptor entry.
End Of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.
Command/Response Indication Bit. This bit determines the state of the C/R bit for the
transmitted frame.
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. It is used for data chaining buffers. ELF is set by the Host. When not chaining,
ELF should be set to a one.
Forward Explicit Congestion Notification Bit. This bit determines the state of the FECN bit
for the transmitted frame.
Backward Explicit Congestion Notification Bit. This bit determines the state of the BECN
bit for the transmitted frame.
Discard Eligibility Bit. This bit determines the state of the DE bit for the transmitted frame.
If in the CT entry TXCONG=1, any frame with DE=1 will not be transmitted, but discarded.
Transmit Interrupt Disable. If this bit is set, no transmit interrupt is generated when
ownership of this descriptor is released back to the host.
The High Order 8 address bits of the buffer pointed to by this descriptor.
This field is written by the Host and unchanged by MK50H28.
When this bit is a zero, the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The host sets the OWNA bit after filling the buffer pointed
to by the descriptor entry. The MK50H28 releases the descriptor after transmitting the
buffer. After the MK50H28 or the Host has relinquished ownership of a buffer, it may not
change any field in the four words that comprise the descriptor entry.
End of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.
Reserved. Must be written as zero
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. It is used for data chaining buffers. ELF is set by the Host. When not chaining,
ELF should be set to a one.
1
2
E
L
F
1
1
Frame
Type
1
0
0
9
0
8
T
N
T
D
I
0
7
DESCRIPTION
DESCRIPTION
0
6
TBADR<23:16>
0
5
0
4
0
3
0
2
0
1
0
0