MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet - Page 26

• Manufacturer Part Number: MK50H28N
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H28
4.1.2.6 Control and Status Register 5 (CSR5)
CSR5 facilitates control and monitoring of modem controls.
RAP<3:1> = 5
26/64
15:06
BIT
5
4
3
2
1
0
XEDGE
RTSEN
NAME
DTRD
DSRD
DTR
DSR
1
5
0
0
1
4
0
Reserved, must be written as zeroes.
Setting this bit causes the TD output to change on the rising edge of TCLK rather than on
the falling edge as indicated in the pin 25 description.
RTS/CTS ENABLE is a READ/WRITE bit used to configure pins 26 and 30. If this bit is
set, pin 26 becomes RTS and pin 30 becomes CTS. RTS is driven low whenever the
MK50H28 has data to transmit and is kept low during transmission. RTS will be
driven high after the closing flag of a signal unit is transmited if either no other frames
are in the FIFO or if the minimum signal unit spacing is higher than 2 (see Mode
Register). The MK50H28 will not begin transmission and TD will remain HIGH if CTS is
high. If RTSEN = 0 then pins 26 and 30 become programmable I/O pins DTR and DSR.
The direction and behavior of DSR and DTR are controlled by the following bits.
DTR DIRECTION is a READ/WRITE bit used to control the direction of the DTR/RTS
pin. If DTRD = 0, the DTR/RTS pin becomes an input pin and the DTR bit reflects the
current value of the pin; if DTRD = 1, the DTR/RTS pin is an output pin controlled by the
DTR bit below.
DSR DIRECTION is a READ/WRITE bit used to control the direction of the DSR/CTS
pin. If DSRD = 0, the DSR/CTS pin becomes an input pin and the DSR bit reflects the
current value of the pin; if DSRD = 1, the DSR/CTS pin is an output pin controlled by the
DSR bit below.
DATA TERMINAL READY is used to control or observe the DTR I/O pin depending on
the value of DTRD. If DTRD = 0, this bit becomes READ ONLY and always equals
the current value of the DTR/RTS pin. If DTRD = 1, this bit becomes READ/WRITE
and any value written to this bit appears on the DTR/RTS pin.
DATA SET READY is used to control or observe the DSR I/O pin depending on the
value of DSRD. If DSRD = 0, this bit becomes READ ONLY and always equals the
current value of the DSR/CTS pin. If DSRD = 1 this bit becomes READ/WRITE and
any value written to this bit appears on the DSR/CTS pin.
1
3
0
1
2
0
1
1
0
1
0
0
0
9
0
0
8
0
0
7
0
DESCRIPTION
0
6
0
0
5
X
E
D
G
E
0
4
R
T
S
E
N
0
3
D
T
R
D
0
2
D
S
R
D
0
1
D
T
R
0
0
D
S
R