PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 3

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS (Continue)
HOST SWING SELECT FUNCTIONS
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
48MHz/FS3
Iref
SDATA
SCLK
VDDPCI
VDDAGP
VDDHTT
VDD48M
AVDD
VDDCPU
VDDREF
VSS
MULTISEL0
Name
0
1
4,10,17,21,2
5,31,37,41,
Number
Programmable Clock Generator for ALI 1681 P4 Chip Sets
11,16
22
38
47
48
28
32
24
36
42
Board Target
Trace/Term Z
1
50Ω
50Ω
Type
B
O
B
P
P
P
P
P
P
P
P
I
At power-up, the FS3 input value is latched. After power-up, this pin acts
as USB output. It has an internal pull-down resistor.
This pin establishes the reference current for the CPU and HTT differential
pairs, it requires a fixed precision resistor tied to ground in order to
establish the appropriate current.
Serial data inputs for serial interface port.
Serial data inputs for serial interface port.
3.3V Power Supply for PCIF, PCI[0:8] clock
3.3V Power Supply for AGP clock.
3.3V Power Supply for HTT clock.
3.3V Power Supply for 48MHz and 24_48MHz clock
3.3V power for internal PLL.
3.3v power supply for CPU[T,C]_[0:1] clocks.
3.3v power supply for REF[0:2] clocks
Ground.
Reference R (Rr)
I
ref
Rr = 221Ω; 1%
Rr = 475Ω; 1%
Iref = 2.32 mA
Iref = 5.0mA
= VDD/(3*Rr)
Description
Output Current
I
I
oh
oh
= 6*IREF
= 7*IREF
PLL202-108
Rev 8/20/02 Page 3
1.0V @ 50Ω
0.7V @ 50Ω
V
oh
@ Z