PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 135

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
Figure 67: AADM Sync Burst Read Cycle (Latching A[15:0] only)
Notes:
1.
2.
3.
A.3.4
A.3.5
April 2008
309823-10
A/DQ[15:0]
ADV#
WAIT
WE#
Diagram shows WAIT as active low (RCR.10=0) and asserted with Data (RCR.8=0).
For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in timing diagram)
Without latching A[MAX:16] in the Sync Read Cycle, the previously latched A[MAX:16] applies.
CLK
CE#
OE#
R311
Synchronous Write Cycles
For synchronous writes, only the address latching cycle(s) are synchronous.
Synchronous address latching is depicted in the timing diagrams for synchronous read
cycles:
The actual write operation (rising WE# edge) is asynchronous and is independent of
CLK. Asynchronous writes are depicted in the timing diagrams for asynchronous write
cycles:
System Boot
Systems that use the AADM mode will boot from the bottom 128k Bytes of device
memory because A[MAX:16] are expected to be grounded in-system. The 128k Byte
boot region is sufficient to perform required boot activities before setting RCR[4] to
enable AADM mode.
•
•
•
•
•
R303
Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address
Cycles)” on page 134
Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address
Cycles)” on page 134
Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135
Figure 63, “AADM Asynchronous Write Cycle (Latching A[MAX:0])” on page 132
Figure 64, “AADM Asynchronous Write Cycle (Latching A[15:0] only)” on page 132
R301
R302
®
Cellular Memory (M18)
A[15:0]
R306
R313
R317
R314
R315
R304
R307
DQ[15:0]
R305
DQ[15:0]
R312
Datasheet
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