PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 74

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

8.5
8.6
8.7
Figure 43: Operating Mode with Correct Command Sequence Example
Figure 44: Operating Mode with Correct Command Sequence Example
Datasheet
74
Address [A]
Address [A]
Data [D/Q]
Data [D/Q]
WE# [W]
WE# [W]
OE# [G]
OE# [G]
While in DPD mode, the read-mode of each partition, configuration registers (RCR and
ECR), and block lock bits, are preserved. Status register is reset to 0080h; i.e., if the
Status register contains error bits, they will be cleared.
Standby
When CE# is deasserted, the device is deselected and placed in standby, substantially
reducing power consumption. In standby, data outputs are placed in high-Z,
independent of the level placed on OE#. If deselected during a Program or Erase
operation, the device continues to consume active power until the operation is
complete. There is no additional latency for subsequent read operations.
Output Disable
When OE# is deasserted with CE# asserted, the device outputs are disabled. Output
pins are placed in a high-impedance state. WAIT is deasserted in AD-muxed devices
and driven to High-Z in non-multiplexed devices.
Bus Cycle Interleaving
When issuing commands to the device, a read operation can occur between the two
write cycles of a 2-cycle command. (See
operation cannot occur between the two write cycles of a 2-cycle command and will
cause a command sequence error (See
Partition A
Partition A
0x20
0x20
Partition B
Partition A
Valid Array Data
0xD0
Figure
Figure 43
Numonyx™ StrataFlash
45).
and
Figure
Partition B
Partition A
0xFF
44) However, a write
®
Cellular Memory (M18)
0xD0
309823-10
April 2008