PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 35

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
Table 8:
April 2008
309823-10
N-ALE
N-RE#
N-RY/BY#
N-WE#
P-CRE
P-MODE#
P[2:1]-CS#
S-CS1#
S-CS2
R-UB#
R-LB#
Power Signals
F-VPP
F[2:1]-VCC
VCCQ
P-VCC
S-VCC
VSS
DU
RFU
Symbol
Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 3
Output
Power
Power
Power
Power
Power
Groun
Type
Input
Input
Input
Input
Input
Input
Input
Input
—
—
of 3)
d
NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-ALE enables addresses to be latched on the rising edge of N-WE#.
NAND READ ENABLE: NAND-specific signal; low-true input.
When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE#
disables the output drivers of the selected NAND die and places the output drivers in High-Z.
NAND READY/BUSY: NAND-specific signal; low-true output.
When low, N-RY/BY# indicates the NAND is busy performing a Read, Program, or Erase
operation. When high, N-RY/BY# indicates the NAND device is ready.
NAND WRITE ENABLE: NAND-specific signal; low-true input.
When low, N-WE# enables Write operations for the enabled NAND die.
PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input.
When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control
Register (P-BCR). When low, P-CRE enables normal Read or Write operations.
PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input.
When low, P-MODE# enables access to the configuration register, and to enter or exit Low-
Power mode. When high, P-MODE# enables normal Read or Write operations.
PSRAM CHIP SELECT: PSRAM-specific signal; low-true input.
When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the
associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT
outputs are placed in a High-Z state.
SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.
When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or
S-CS2 is deasserted, the SRAM die is deselected.
RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs.
When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read
and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0].
FLASH PROGRAM/ERASE VOLTAGE: Flash specific.
F-VPP supplies program or erase power to the flash die.
FLASH CORE POWER SUPPLY: Flash specific.
F[2:1]-VCC supplies the core power to the flash die.
For NOR/NAND stacked device, F1-VCC is dedicated for all NOR dies, F2-VCC is dedicated for all
NAND dies.
I/O POWER SUPPLY: Global device I/O power.
VCCQ supplies the device input/output driver voltage.
PSRAM CORE POWER SUPPLY: PSRAM specific.
P-VCC supplies the core power to the PSRAM die.
SRAM POWER SUPPLY: SRAM specific.
S-VCC supplies the core power to the SRAM die.
DEVICE GROUND: Global ground reference for all signals and power supplies.
Connect all VSS balls to system ground. Do not float any VSS connections.
DO NOT USE:
Ball should not be connected to any power supplies, signals, or other balls. Ball can be left
floating.
RESERVED for FUTURE USE:
Reserved by Numonyx for future device functionality and enhancement. Ball must be left
floating.
®
• P1-CS# is dedicated to PSRAM die #1.
• P2-CS# IS dedicated to PSRAM die #2. Otherwise, any unused PSRAM chip select should be
Cellular Memory (M18)
treated as RFU.
Signal Descriptions
Datasheet
Notes
1, 2
1, 4
1, 3
1, 3
1, 4
1
1
1
1
5
1
1
35