PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 43

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
6.0
6.1
6.1.1
Table 12: Power-Up/Down Sequence
Note:
6.1.2
6.1.3
April 2008
309823-10
Power Supply
V
Voltage
V
V
CCQ(min)
CC(min)
PP(min)
Electrical Characteristics
Initialization
Proper device initialization and operation is dependent on the power-up/down
sequence, reset procedure, and adequate power-supply decoupling. The following
sections describe each of these areas.
Power-Up/Down Characteristics
To prevent conditions that could result in spurious program or erase operations, the
power-up/power-down sequence shown in
power supply must reach its minimum voltage range before applying/removing the
next supply voltage.
* Power supplies connected or sequenced together.
Device inputs must not be driven until all supply voltages reach their minimum range.
RST# should be low during power transitions.
If VCCQ is below VLKOQ, the device is reset.
Reset Characteristics
During power-up and power-down, RST#should be asserted to prevent spurious
program or erase operations. While RST#is low, device operations are disabled; all
inputs such as address and control are ignored; and all outputs such as data and WAIT
are placed in High-Z. Invalid bus conditions are effectively masked out.
Upon power-up, RST#can be deasserted after tVCCPH, allowing the device to exit from
reset. Upon exiting from reset, the device defaults to asynchronous Read Array mode,
and the Status Register defaults to 0080h. Array data is available after tPHQV, or a bus-
write cycle can begin after tPHWL.
If RST#is asserted during a program or erase operation, the operation will abort and
array contents at that location will be invalid.
For proper system initialization, connect RST#to the low-true reset signal that asserts
whenever the processor is reset. This will ensure the flash device is in the expected
read mode (i.e., Read Array) upon startup.
Power Supply Decoupling
High-speed flash memories require adequate power-supply decoupling to prevent
external transient noise from affecting device operations, and to prevent internally-
generated transient noise from affecting other devices in the system.
2nd
3rd
1st
®
Cellular Memory (M18)
2nd*
1st
Power-Up Sequence
1st*
2nd
Sequencing not
required*
Table 12
2nd
3rd
1st
is recommended. Note that each
1st*
2nd
Power-Down Sequence
2nd*
1st
Sequencing not
required*
Datasheet
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