PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 26

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

4.2
Table 7:
Datasheet
26
Address and Data Signals, Non-Mux
A[MAX: 0]
DQ[15:0]
F-ADV#
Address and Data Signals, AD-Mux
A[MAX:16]
AD[15:0]
A[15:0]
Symbol
Output
Input /
Output
Input/
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 1 of 4)
Type
Input
Input
Input
Input
Signal Descriptions, x16D
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
Unused address inputs should be treated as RFU.
DATA INPUT/OUTPUTS: Global device signals.
DQ[15:0] are used to input commands and write-data during Write cycles, and to output read-
data during Read cycles. During NAND accesses, DQ[7:0] are used to input commands, address-
data, and write-data, and to output read-data.
Data signals are High-Z when the device is deselected or its output is disabled.
FLASH ADDRESS VALID: Flash-specific signal; low-true input.
During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,
or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108
MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to
133 MHz.
In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV# or
continuously flows through while F-ADV# is low.
ADDRESS: Global device signals.
Shared address inputs for all Flash and SRAM memory die during Read and Write operations.
Unused address inputs should be treated as RFU.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux flash and SRAM lower address
and data signals; LPSDRAM data signals.
During AD-Mux flash and SRAM Write cycles, AD[15:0] are used to input the lower address
followed by commands or write-data.
During AD-Mux flash Read cycles, AD[15:0] are used to input the lower address followed by
read-data output.
During LPSDRAM accesses, AD[15:0] are used to input commands and write-data during Write
cycles or to output read-data during Read cycles.
During NAND accesses, AD[7:0] are used to input commands, address, or write-data, and to
output read-data.
AD[15:0] are High-Z when the flash or SRAM is deselected or its output is disabled.
RFU, except for DRAM.
• 4-Gbit: AMAX = A27
• 2-Gbit: AMAX = A26
• 1-Gbit: AMAX = A25
• 512-Mbit: AMAX = A24
• 256-Mbit: AMAX = A23
• 128-Mbit: AMAX = A22
• A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM.
• A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM.
• A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM.
• 4-Gbit: AMAX = A27
• 2-Gbit: AMAX = A26
• 1-Gbit: AMAX = A25
• 512-Mbit: AMAX = A24
• 256-Mbit: AMAX = A23
• 128-Mbit: AMAX = A22
Signal Descriptions
Numonyx™ StrataFlash
®
Cellular Memory (M18)
309823-10
April 2008
Notes
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