MC68306 Motorola, MC68306 Datasheet - Page 119

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

The receiver detects the beginning of a break in the middle of a character if the break
persists through the next character time. When the break begins in the middle of a
character, the receiver places the damaged character in the receiver first-in-first-out
(FIFO) stack and sets the corresponding error conditions and RxRDY bit in the DUSR.
Then, if the break persists until the next character time, the receiver places an all-zero
character into the receiver FIFO and sets the corresponding RB and RxRDY bits in the
DUSR.
6.3.2.3 FIFO STACK. The FIFO stack is used in each channel's receiver buffer logic. The
stack consists of three receiver holding registers. The receive buffer consists of the FIFO
and a receiver shift register connected to the RxDx (refer to Figure 6-4). Data is
assembled in the receiver shift register and loaded into the top empty receiver holding
MOTOROLA
RECEIVER
OVERRUN
NOTES:
ENABLED
1. Timing shown for MR1(7) = 1
2. Timing shown for OPCR(4) = 1 and MR1(6) = 0
3. R = Read
4. C = Received Character
RxRDY
FFULL
(OP0)
RTS
(SR1)
(SR0)
(SR4)
OPR(0) = 1
RxD
CS
N
1
C1
STATUS DATA
R
C1
Figure 6-6. Receiver Timing Diagram
R
C2
MC68306 USER'S MANUAL
C3
C4
C5
LOST
C5
STATUS DATA
C2
R
C6, C7, C8 ARE LOST
R
C6
R R
RESET BY COMMAND
C3
R R
C7
STATUS DATA
C4
C8
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