MC68306 Motorola, MC68306 Datasheet - Page 28

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

additional information about the interaction between HALT and RESET , refer to 3.5 Reset
Operation and for more information on HALT and BERR , refer to 3.4 Bus Error and Halt
Operation.
Processor assertion of HALT indicates a double bus fault condition. This condition is
unrecoverable; the MC68306 must be externally reset to resume operation.
2.1.12 Read/Write (R/
This three-state, bi-directional signal defines the data bus transfer as a read or write cycle.
The R/W signal relates to the data strobe signals described in the following paragraphs.
2.1.13 Upper And Lower Data Strobes (
These three-state, bi-directional signals and R/W control the flow of data on the data bus.
Table 2-9 lists the combinations of these signals, the corresponding data on the bus, and
the OE, LW, and UW signals. When the R/W line is high, the processor reads from the
data bus. When the R/W line is low, the processor drives the data bus. When another bus
master controls the bus, the UDS, LDS, and R/ W pins become inputs and the OE, LW,
and UW signals are still decoded as shown in Table 2-9.
2.1.14 Upper-Byte Write (
This signal is a combination of R/W low and UDS low for writing the upper-byte of a 16-bit
port. This signal simplifies memory system design by explicitly signalling that data is valid
on the upper portion of the data bus on a write operation. UW is also decoded for external
bus masters.
2-8
*These conditions are a result of current implementation and may not appear
on future devices.
UDS
High
High
High
Low
Low
Low
Low
High
High
High
LDS
Low
Low
Low
Low
Table 2-9. Data Strobe Control of Data Bus
High
High
High
R/
Low
Low
Low
—
W
W
)
UW
Valid Data Bits
Valid Data Bits
Valid Data Bits
Valid Data Bits
Valid Data Bits
No Valid Data
No Valid Data
MC68306 USER'S MANUAL
D8–D15
15–8
15–8
15–8
7–0*
15–8
)
Valid Data Bits
Valid Data Bits
Valid Data Bits
Valid Data Bits
Valid Data Bits
No Valid Data
No Valid Data
UDS
D0–D7
15–8*
7–0
7–0
7–0
7–0
,
LDS
)
High
High
High
High
Low
Low
Low
OE
High
High
High
High
High
Low
Low
UW
MOTOROLA
High
High
High
High
High
Low
Low
LW