MC68306 Motorola, MC68306 Datasheet - Page 44

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

3.2 BUS ARBITRATION
Bus arbitration is a technique used by bus master devices to request, to be granted, and
to acknowledge bus mastership. Bus arbitration consists of the following:
Figure 3-12 is a flowchart showing the bus arbitration cycle of the EC000 core. Figure 3-
13 is a timing diagram of the bus arbitration cycle charted in Figure 3-12. This technique
allows processing of bus requests during data transfer cycles.
3-12
IPL2–IPL0
*
FC2–FC0
1. Asserting a bus mastership request
2. Receiving a grant indicating that the bus is available at the end of the current cycle
3. Acknowledging that mastership has been assumed
IPL2–IPL0 SAMPLED
IPL2–IPL0 TRANSITION
Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not
recognize anything on data lines D8 through D15 at this time.
IPL2–IPL0 VALID INTERNALLY
A23–A4
D15–D8
DTACK
D7–D0
A3–A1
IACK
UDS
LDS
R/W
CLK
AS
*
S0 S1 S2 S3 S4 S5 S6 S7
LAST BUS CYCLE OF INSTRUCTION
Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram
(READ OR WRITE)
MC68306 USER'S MANUAL
STACK
(SSP)
PCL
S0 S1 S2 S3 S4
(VECTOR NUMBER
SW SW
ACQUISITION)
IACK CYCLE
S5 S6 S7 S0 S1 S2 S3 S4 S5 S6
STACK AND
VECTOR
FETCH
MOTOROLA