MC68306 Motorola, MC68306 Datasheet - Page 61

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

The possible bus cycle terminations can be summarized as follows (case numbers refer to
Table 3-1).
Table 3-1 shows the details of the resulting bus cycle terminations for various
combinations of signal sequences.
LEGEND:
MOTOROLA
Normal Termination:
Halt Termination:
Bus Error Termination: BERR is asserted in lieu of, coincident with, or preceding
Retry Termination:
NOTE: All operations are subject to relevant setup and hold times.
NA — Signal not asserted in this bus state
Case
No.
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
1
2
3
4
5
6
Table 3-1.
Control
DTACK
DTACK
DTACK
DTACK
DTACK
DTACK
Signal
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
DTACK is asserted. BERR and HALT remain negated (case 1).
HALT is asserted coincident with or preceding DTACK, and
BERR remains negated (case 2).
DTACK (case 3).
HALT and BERR asserted in lieu of, coincident with, or before
DTACK (case 5).
DTACK
Asserted on Rising
A/S
A/S
NA
NA
NA
NA
NA
NA
NA
NA
Edge of State
N
A
A
X
A
A
X
A
A
MC68306 USER'S MANUAL
,
BERR
N+2
NA
NA
NA
NA
S
X
S
S
X
S
S
A
X
S
S
S
A
A
, and
Normal cycle terminate and continue.
Normal cycle terminate and halt. Continue
when HALT negated.
Terminate and take bus error trap.
Normal cycle terminate and continue.
Terminate and retry when HALT removed.
Normal cycle terminate and continue.
HALT
EC000 Core Results
Assertion Results
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