MC68306 Motorola, MC68306 Datasheet - Page 139

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

IEC2, IEC1, IEC0—Input Enable Control
6.4.1.10 INTERRUPT STATUS REGISTER (DUISR). The DUISR provides status for all
potential interrupt sources. The contents of this register are masked by the DUIMR. If a
flag in the DUISR is set and the corresponding bit in DUIMR is also set, the IRQ output is
asserted. If the corresponding bit in the DUIMR is cleared, the state of the bit in the
DUISR has no effect on the output.
COS—Change-of-State
MOTOROLA
1 = DUISR bit 7 will be set and an interrupt will be generated when the
0 = Setting the corresponding bit in the DUIPCR has no effect on DUISR bit 7.
1 = A change-of-state has occurred at one of the IPx inputs and has been selected to
0 = No selected COSx in the DUIPCR.
corresponding bit in the DUIPCR (COS2, COS1, or COS0) is set by an external
transition on the IPx input (if bit 7 of the interrupt mask register (DUIMR) is set to
enable interrupts).
cause an interrupt by programming bit 2, 1 and/or bit 0 of the DUACR.
MISC2
0
0
0
0
1
1
1
1
The IDUMR does not mask reading of the DUISR. True status
is provided regardless of the contents of DUIMR. The contents
of DUISR are cleared when the serial module is reset.
Table 6-10. Counter/Timer Mode and Source Select Bits
MISC1
0
0
1
1
0
0
1
1
DUISR
Read Only
RESET:
COS
7
0
MISC0
DBB
6
0
0
1
0
1
0
1
0
1
MC68306 USER'S MANUAL
RxRDYB TxRDYB CTR/TM
5
0
Mode Command
Counter
Counter
Counter
Counter
4
0
NOTE
Timer
Timer
Timer
Timer
_RDY
3
R
1
DBA
2
0
Clock Source Select Command
External Clock Divided by 16
RxRDYA TxRDYA
External–IP2 Divided by 16
Crystal or External Clock
Crystal or External Clock
1
0
External–IP2
External–IP2
0
0
TxCA
TxCB
6-31