MC68306 Motorola, MC68306 Datasheet - Page 58

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

The processor terminates the bus cycle, and remains in this state until HALT is negated.
Then the processor retries the preceding cycle using the same function codes, address,
and data (for a write operation). BERR should be negated at least one clock cycle before
HALT is negated.
3.4.3 Halt Operation
HALT
device, the processor halts and remains halted as long as the signal remains asserted, as
shown in Figure 3-26.
While the processor is halted, bus arbitration is performed as usual. Should a bus error
occur while HALT is asserted, the processor performs the retry operation previously
described.
3-26
LDS/UDS
FC2-FC0
D15–D0
A23–A1
DTACK
BERR
HALT
CLK
R/W
performs a halt/run/single-step operation. When HALT is asserted by an external
AS
S0
To guarantee that the entire read-modify-write cycle runs
correctly and that the write portion of the operation is
performed without negating the address strobe, the processor
does not retry a read-modify-write cycle. When BERR occurs
during a read-modify-write operation, a bus error operation is
performed whether or not HALT is asserted.
If a RESET instruction is executed while HALT is asserted, the
CPU will be reset.
S2
READ
Figure 3-25. Retry Bus Cycle Timing Diagram
S4
S6
S8
MC68306 USER'S MANUAL
1 CLOCK PERIOD
NOTE
NOTE
HALT
S0
S2
RETRY
S4
S6
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