MC68306 Motorola, MC68306 Datasheet - Page 172

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MC68306

Manufacturer Part Number
MC68306
Description
Integrated EC000 Processor
Manufacturer
Motorola
Datasheet

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8-8
NOTES:
ASYNCHRONOUS
3. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees
HALT / RESET
of S2 (specification #20A).
their recognition at the next falling edge of the clock.
DATA OUT
BERR / BR
LDS / UDS
(NOTE 1)
FC2–FC0
(NOTE 2)
(NOTE 3)
(NOTE 2)
UW, LW
CLKOUT
INPUTS
DTACK
A23–A1
R/W
AS
13
Figure 8-4. Write Cycle Timing Diagram
S0
17
15
7
18
S1
8
11A
32
47
MC68306 USER'S MANUAL
15A
55
23
S2
21
9
6
26
11
S3
20
20A
48
56
22
S4
47
14
9
S5
32
47
47
47
14A
S6
9A
S7
12
30
28
53
25
12A
MOTOROLA

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