MT48H16M16LF MICRON [Micron Technology], MT48H16M16LF Datasheet - Page 16

• Manufacturer Part Number: MT48H16M16LF
• Description: 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
• Manufacturer: MICRON [Micron Technology]

Figure 7:
Operating Mode
Write Burst Mode
Extended Mode Register (EMR)
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
CAS Latency
COMMAND
COMMAND
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-
location accesses.
The low-power EMR controls the functions beyond those controlled by the MR. These
additional functions are special features of the mobile device. They include tempera-
ture-compensated self refresh (TCSR) control, partial-array self refresh (PASR), and
output drive strength.
The low-power EMR is programmed via the MODE REGISTER SET command and
retains the stored information until it is programmed again or the device loses power.
CLK
CLK
DQ
DQ
READ
READ
T0
T0
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
CL = 2
NOP
NOP
T1
T1
16
t
t AC
LZ
CL = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
NOP
T3
T3
D
t OH
OUT
DON’T CARE
UNDEFINED
©2006 Micron Technology, Inc. All rights reserved.
Register Definition
T4