MT48H16M16LF MICRON [Micron Technology], MT48H16M16LF Datasheet - Page 26

• Manufacturer Part Number: MT48H16M16LF
• Description: 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
• Manufacturer: MICRON [Micron Technology]

Figure 13:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
Random READ Accesses
Note:
COMMAND
COMMAND
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 14 on page 27 and
Figure 15 on page 28. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
ADDRESS
ADDRESS
Each READ command may be to either bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
BANK,
T0
COL n
BANK,
COL n
READ
READ
CL = 2
T1
T1
BANK,
BANK,
READ
COL a
READ
COL a
CL = 3
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
26
T2
BANK,
T2
COL x
BANK,
READ
READ
COL x
D
OUT
n
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T3
T3
BANK,
COL m
READ
READ
BANK,
COL m
D
D
OUT
OUT
a
n
T4
T4
NOP
NOP
D
D
OUT
OUT
x
a
T5
T5
NOP
NOP
D
D
OUT
m
OUT
x
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T6
NOP
D
OUT
m
Operations