MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 11

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

CAS Latency
the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
two or three clocks.
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in
Figure 2. Table 2 below indicates the operating frequen-
cies at which each CAS latency setting can be used.
eration or incompatibility with future versions
may result.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, between
If a READ command is registered at clock edge n, and
Reserved states should not be used as unknown op-
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency = 2
CAS Latency
Figure 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
T2
T2
NOP
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
11
Operating Mode
and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to both READ and
WRITE bursts.
because unknown operation or incompatibility with fu-
ture versions may result.
Write Burst Mode
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
SPEED
The normal operating mode is selected by setting M7
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via
-7E
-75
-8E
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LATENCY = 2
≤ 133
≤ 100
≤ 100
CAS Latency
ALLOWABLE OPERATING
CAS
128Mb: x4, x8, x16
FREQUENCY (MHz)
Table 2
LATENCY = 3
©2001, Micron Technology, Inc.
SDRAM
≤ 143
≤ 133
≤ 125
CAS