MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 41

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTES: 1. No maximum time limit for Self Refresh.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
DQML, DQMH
SYMBOL* MIN
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
A0-A9, A11
BA0, BA1
DQM/
2.
CKE
A10
CLK
DQ
t
XSR requires minimum of two clocks regardless of frequency or timing.
0.8
1.5
2.5
2.5
7.5
0.8
7
High-Z
Precharge all
t CKS
active banks
t CMS
-7E
t
SINGLE BANK
AS
ALL BANKS
PRECHARGE
BANK(S)
MAX
T0
t CKH
t CMH
t
AH
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
10
-75
t RP
MAX
T1
NOP
t CH
Enter self refresh mode
MIN
10
1
2
3
3
8
1
-8E
t CKS
t CL
MAX
SELF REFRESH MODE
REFRESH
AUTO
CLK stable prior to exiting
T2
t
RAS max applies to non-Self Refresh mode.
UNITS
self refresh mode
≥
ns
ns
ns
ns
ns
ns
ns
t RAS min
(
(
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(
)
)
(
(
)
)
)
(
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(
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(
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(
)
)
(
(
)
(
)
)
41
1
SYMBOL*
t
t
t
t
t
t
CKS
CMH
CMS
RAS
RP
XSR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(Restart refresh time base)
Exit self refresh mode
Tn + 1
MIN
1.5
0.8
1.5
37
15
75
-7E
t XSR
NOP
120,000
MAX
(
(
(
(
(
(
(
(
)
(
)
(
(
)
(
)
(
)
(
)
)
)
)
(
)
)
)
)
)
)
(
(
(
(
(
(
(
(
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(
)
(
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(
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(
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(
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)
)
(
)
)
128Mb: x4, x8, x16
or COMMAND
INHIBIT
MIN
To + 1
1.5
0.8
1.5
44
20
75
-75
120,000
MAX
MIN
50
20
80
To + 2
2
1
2
©2001, Micron Technology, Inc.
REFRESH
AUTO
SDRAM
-8E
120,000
DON’T CARE
MAX
UNITS
ns
ns
ns
ns
ns
ns