MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 26

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

CONCURRENT AUTO PRECHARGE
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRECHARGE.
Micron SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
An access command (READ or WRITE) to another
precharge): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to
Internal
States
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
READ With Auto Precharge Interrupted by a WRITE
READ With Auto Precharge Interrupted by a READ
NOTE: DQM is LOW.
COMMAND
COMMAND
ADDRESS
BANK m
ADDRESS
BANK n
BANK m
BANK n
DQM
CLK
DQ
CLK
DQ
1
Active
Page
READ - AP
Page Active
BANK n,
T0
NOP
BANK n
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
Page Active
T1
NOP
READ with Burst of 4
CAS Latency = 3 (BANK n)
OUT
-a+1 from contending with D
Figure 25
Figure 24
T2
T2
NOP
NOP
26
BANK m,
READ - AP
T3
BANK m
COL d
T3
D
NOP
OUT
2. Interrupted by a WRITE (with or without auto
a
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).
BANK m,
WRITE - AP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COL d
T4
BANK m
T4
D
NOP
d
IN
IN
Interrupt Burst, Precharge
D
WRITE with Burst of 4
-d at T4.
OUT
a
t
RP - BANK n
T5
T5
d + 1
NOP
NOP
D
IN
D
a + 1
OUT
t
RP - BANK n
T6
T6
d + 2
NOP
128Mb: x4, x8, x16
NOP
D
IN
D
OUT
d
DON’T CARE
Idle
T7
t WR - BANK m
d + 3
T7
NOP
D
NOP
t RP - BANK m
IN
Write-Back
Precharge
D
d + 1
OUT
Idle
©2001, Micron Technology, Inc.
SDRAM