MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 17

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

This is shown in Figure 7 for CAS latencies of two and
three; data element n + 3 is either the last of a burst of four
or the last desired of a longer burst. The 128Mb SDRAM
uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architec-
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
COMMAND
COMMAND
ADDRESS
ADDRESS
NOTE:
CLK
CLK
DQ
DQ
T0
BANK,
T0
COL n
BANK,
Each READ command may be to any bank. DQM is LOW.
READ
COL n
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
Consecutive READ Bursts
T2
T2
NOP
NOP
D
OUT
n
Figure 7
T3
T3
NOP
NOP
17
D
n + 1
D
OUT
OUT
n
ture. A READ command can be initiated on any clock
cycle following a previous READ command. Full-speed
random read accesses can be performed to the same
bank, as shown in Figure 8, or each subsequent READ
may be performed to a different bank.
T4
T4
BANK,
BANK,
READ
READ
COL b
COL b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 1 cycle
n + 2
n + 1
D
D
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
n + 2
n + 3
D
D
OUT
OUT
128Mb: x4, x8, x16
T6
T6
NOP
NOP
n + 3
D
D
OUT
OUT
b
DON’T CARE
T7
NOP
D
©2001, Micron Technology, Inc.
OUT
b
SDRAM