MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 36

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

NOTES
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11. AC timing and I
12. Other input signals are allowed to transition no more
13. I
14. Timing actually specified by
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
All voltages referenced to V
This parameter is sampled. V
f = 1 MHz, T
I
Specified values are obtained with minimum cycle
time and the outputs open.
Enables on-chip refresh and address counters.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C ≤ T
40°C ≤ T
An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (V
must be powered up simultaneously. V
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the
AC characteristics assume
In addition to meeting the transition rate specifica-
tion, the clock and CKE must transit between V
V
Outputs measured at 1.5V with equivalent load:
t
open circuit condition; it is not a reference to V
V
going High-Z.
timing referenced to 1.5V crossover point. If the in-
put transition time is longer than 1 ns, then the
timing is referenced at V
no longer at the 1.5V crossover point. Refer to Micron
Technical Note TN-48-09 for more details.
than once every two clocks and are otherwise at valid
V
erly initialized.
as a reference only at minimum cycle rate.
HZ defines the time at which the output achieves the
DD
DD
IL
OL
IH
(or between V
. The last valid data element will meet
is dependent on output loading and cycle rates.
or V
specifications are tested after the device is prop-
t
REF refresh requirement is exceeded.
IL
A
levels.
≤ +85°C for IT parts) is ensured.
A
= 25°C; pin under test biased at 1.4V.
DD
Q
IL
tests have V
and V
IH
IL
) in a monotonic manner.
(MAX) and V
t
SS
T = 1ns.
IL
t
.
CKS; clock(s) specified
= 0V and V
DD
50pF
, V
A
≤ +70°C and -
DD
DD
IH
SS
Q = +3.3V;
IH
t
(MIN) and
and V
OH before
and V
= 3V, with
IH
OH
DD
and
SS
or
Q
Q
36
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality
18. The I
19. Address transitions average one transition every two
20. CLK must be toggled a minimum of two times during
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8E, CL = 2 and
33. CKE is HIGH during refresh command period
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
specified as a reference only at minimum cycle rate.
and are not dependent on any timing parameter.
tionally according to the amount of frequency alter-
ation for the test condition.
clocks.
this period.
-7E .
≤ 3ns, and the pulse width cannot be greater than one
third of the cycle rate. V
for a pulse width ≤ 3ns.
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including
and PRECHARGE commands). CKE may be used to
reduce the data rate.
budget (
for -8E after the first clock delay, after the last WRITE
is executed. May not exceed limit set for precharge
mode.
t
guaranteed by design.
t
t
ally a nominal value and does not result in a fail
value.
IH
AC for -75/-7E at CL = 3 with no load is 4.6ns and is
CK = 7.5ns; for -7E, CL = 2 and
RFC (MIN) else CKE is LOW. The I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
overshoot: V
DD
t
t
current will increase or decrease propor-
RP) begins 7ns for -7E, 7.5ns for -75, and 7ns
CK = 10ns for -8E and
IH
(MAX) = V
128Mb: x4, x8, x16
t
CK = 10ns; for -75, CL = 3 and
IL
undershoot: V
DD
t
Q + 2V for a pulse width
t
WR.
t
WR plus
CK = 7.5ns for -75 and
t
CK = 7.5ns.
DD
©2001, Micron Technology, Inc.
SDRAM
6 limit is actu-
IL
t
RP; clock(s)
(MIN) = -2V
t
WR,