MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 25

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

CLOCK SUSPEND
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the
time of a suspended internal clock edge is ignored; any
data present on the DQ pins remains driven; and burst
counters are not incremented, as long as the clock is
suspended. (See examples in Figures 22 and 23.)
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
COMMAND
INTERNAL
ADDRESS
The clock suspend mode occurs when a column ac-
For each positive clock edge on which CKE is sampled
Clock Suspend During WRITE Burst
NOTE: For this example, burst length = 4 or greater, and DM
CLOCK
CLK
CKE
D
IN
is LOW.
NOP
T0
BANK,
WRITE
COL n
T1
D
n
IN
Figure 22
T2
T3
NOP
n + 1
T4
D
IN
T5
NOP
n + 2
D
IN
25
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the programmed
burst length and sequence, just as in the normal mode of
operation (M9 = 0).
COMMAND
INTERNAL
ADDRESS
CLOCK
Clock suspend mode is exited by registering CKE
The burst read/single write mode is entered by pro-
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
Clock Suspend During READ Burst
CKE
CLK
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQM is LOW.
T0
BANK,
COL n
READ
T1
NOP
Figure 23
128Mb: x4, x8, x16
T2
NOP
D
OUT
n
T3
n + 1
D
OUT
T4
NOP
©2001, Micron Technology, Inc.
SDRAM
T5
NOP
n + 2
D
OUT
DON’T CARE
T6
NOP
D
n + 3
OUT