MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 52

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
DQML, DQMH
SYMBOL*
COMMAND
t
t
t
t
t
t
t
t
t
A0-A9, A11
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
BA0, BA1
DQM /
CLK
CKE
A10
DQ
2. x16: A9 and A11 = “Don’t Care”
3. WRITE command not allowed else
t CMS
t CKS
x8: A11 = “Don’t Care”
t AS
t AS
t AS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
7
ACTIVE
T0
ROW
ROW
BANK
t CMH
-7E
t CKH
t AH
t AH
t AH
MAX
t RCD
t RAS
t RC
t CK
T1
NOP 3
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
-75
SINGLE WRITE – WITH AUTO PRECHARGE
MAX
t CL
NOP 3
T2
t CH
MIN
10
1
2
3
3
8
1
2
1
-8E
t
RAS would be violated.
MAX
NOP 3
T3
ENABLE AUTO PRECHARGE
UNITS
t CMS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t DS
COLUMN m 2
BANK
WRITE
T4
D
IN
t CMH
t DH
m
52
t WR
SYMBOL*
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1 CLK +
MIN
7ns
1.5
0.8
1.5
37
60
15
15
T6
NOP
-7E
120,000
MAX
t RP
128Mb: x4, x8, x16
1 CLK +
T7
NOP
7.5ns
MIN
1
1.5
0.8
1.5
44
66
20
20
-75
120,000
MAX
ACTIVE
ROW
ROW
BANK
T8
1 CLK +
MIN
7ns
50
70
20
20
2
1
2
©2001, Micron Technology, Inc.
SDRAM
DON’T CARE
-8E
120,000
MAX
T9
NOP
UNITS
ns
ns
ns
ns
ns
ns
ns
–