MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 48

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

DQML, DQMH
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
COMMAND
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
A0-A9, A11
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
BA0, BA1
DQM /
CKE
A10
CLK
DQ
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
t CMS t CMH
t CKS
0.8
1.5
2.5
2.5
7.5
0.8
t AS
t AS
t AS
7
ACTIVE
T0
ROW
ROW
BANK
-7E
t CKH
t AH
t AH
t AH
MAX
5.4
5.4
t RCD
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
10
T1
NOP
-75
MAX
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
5.4
6
t CMS
t CL
COLUMN m 2
MIN
T2
READ
BANK
10
1
2
3
3
8
1
t CMH
t CH
READ – DQM OPERATION
-8E
CAS Latency
MAX
6
6
T3
NOP
UNITS
t
LZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
t AC
48
T4
NOP
t OH
D
t HZ
SYMBOL* MIN
t
t
t
t
t
t
t
t
OUT
CKS
CMH
CMS
HZ(3)
HZ(2)
LZ
OH
RCD
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t
LZ
1.5
0.8
1.5
15
t AC
1
3
1
-7E
MAX
5.4
5.4
T6
128Mb: x4, x8, x16
NOP
D
t OH
OUT
t AC
MIN
1.5
0.8
1.5
20
1
3
m + 2
-75
MAX
5.4
6
T7
NOP
D
OUT
t OH
t HZ
m + 3
MIN
20
2
1
2
1
3
©2001, Micron Technology, Inc.
SDRAM
-8E
MAX
T8
NOP
6
6
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns