MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 47

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

DQML, DQMH
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
COMMAND
A0-A9, A11
SYMBOL* MNI
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
BA0, BA1
DQM /
CLK
CKE
A10
DQ
2. x16: A9 and A11 = “Don’t Care”
3. Page left open; no
t CKS
t CMS
x8: A11 = “Don’t Care”
t AS
t AS
t AS
0.8
1.5
2.5
2.5
7.5
0.8
ACTIVE
7
BANK
T0
ROW
ROW
t CKH
t CMH
-7E
t AH
t AH
t AH
MAX
t RCD
5.4
5.4
t CL
T1
NOP
MIN
0.8
1.5
2.5
2.5
7.5
0.8
t CH
10
t
RP.
-75
t CMS
MAX
t CK
COLUMN m 2
5.4
6
T2
BANK
READ
t CMH
CAS Latency
MIN
10
1
2
3
3
8
1
READ – FULL-PAGE BURST
-8E
T3
MAX
NOP
t LZ
6
6
t AC
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
T4
D
NOP
OUT
t OH
m
1,024 (x8) locations within same row
2,048 (x4) locations within same row
47
t AC
512 (x16) locations within same row
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
D
SYMBOL* MIN
t
t
t
t
t
t
t
t
T5
CKS
CMH
CMS
HZ(3)
HZ(2)
LZ
OH
RCD
OUT
NOP
t OH
m+1
Full page completed
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t AC
D
T6
1.5
0.8
1.5
15
NOP
OUT
1
3
t OH
t AC
1
m+2
-7E
(
(
(
(
(
(
)
(
)
(
)
(
)
(
(
)
(
(
(
)
)
)
)
)
)
(
(
(
(
(
(
)
(
)
(
)
)
)
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
MAX
(
(
(
(
)
(
)
(
)
)
)
)
5.4
5.4
Tn + 1
128Mb: x4, x8, x16
D
NOP
OUT
t OH
MIN
m-1
1.5
0.8
1.5
20
1
3
t AC
-75
MAX
BURST TERM
Tn + 2
3
5.4
6
D
OUT
t OH
m
t AC
MIN
20
2
1
2
1
3
©2001, Micron Technology, Inc.
SDRAM
-8E
Tn + 3
D
OUT
NOP
MAX
DON’T CARE
UNDEFINED
t OH
m+1
t HZ
6
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Tn + 4
NOP