DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 20

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
10.4.5 Data parity/data enable
10.7.1 LVDS DDR clock
10.5 Interrupt controller
10.6 General-purpose IO pins
10.7 Input clock
The ALIGN pins can be used in several ways:
The DAC1617D1G0 incorporates an interrupt controller that makes notifying a
host-controller in case of an internal event. The INTR-signal can be made available on
one of the IO pins. The polarity on the IO pins is programmable.
The internal event that must be tracked and generates an interrupt can be selected using
the INTR_EN register (see Table 45). Two types of interrupt sources are considered:
The selected event that has invoked the interrupt can be determined using the
INTR_FLAGS register (see Table 47). The flags and the INTR signal are reinitialized by
setting the INTR_CLEAR control bit in register INTR_CTRL (see Table 45).
The DAC1617D1G0 provides two general-purpose pins, IO0 and IO1. These pins can be
used to observe the interrupt signal (INTR) or other internal signals (internal clocks, LVDS
data, etc.). These pins can also be used as generic outputs to control external devices.
The internal signals that must be observed on these pins are selected using registers
IO_MUX0, IO_MUX1, and IO_MUX2 (see Table 63 and Table 64).
The DAC1617D1G0 operates with two clocks, one for the LVDS DDR interface and one
for the DAC core.
The LVDS DDR clock can be interfaced as shown in Figure 10 because the clock buffer
contains a 100  internal resistor.
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As datastream start flag for Multiple Devices Synchronization (see Section 10.13).
As LVDS data enable which can be used to insert a DC level into the datastream. The
SEL_EN bits in register LD_CNTRL (see Table 60) enable the programming of this
mode. The DC level for both channels is selected using registers I_DC_LVL and
Q_DC_LVL (see Table 62)
As parity bit for the LD[15:0] to detect disruptions at the LVDS-input port bit PARITYC
in register LD_CNTRL (see Table 60) enabling the control of this mode. A Parity error
can generate an interrupt (INTR) reported on either IO0 or IO1 pin
The ready-indicators (MAQ_RDY_B, MAQ_RDY_A, AUTO_CAL_RDY, and
AUTO_DL_RDY; register INTR_FLAGS; see Table Table 47) notify the host-interface
that the corresponding process (invoked by the host interface) has been finalized
The error flags indicate that a failure has been detected. For example, on the
LVDS-interface it is possible to check for parity errors and/or to monitor if the internal
timing of the LVDS clock delay has changed since the calibration. Errors like these
can result in critical timings within the Clock Domain Interface (CDI) which transfers
the data from the LCLK to the DCLK domain
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
DAC1617D1G0
© IDT 2012. All rights reserved.
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