DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 68

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DAC1617D1G0HN

Manufacturer Part Number
DAC1617D1G0HN
Description
Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Integrated Device Technology
Table 57.
Default values are shown highlighted.
Table 58.
Default values are shown highlighted.
Table 59.
Default values are shown highlighted.
Table 60.
Default values are shown highlighted.
DAC1617D1G0 3
Preliminary data sheet
Address
04h
05h
Bit
7 to 0
Address
08h
09h
Bit
7
6
5 to 4
3
Symbol
DCMSU_PREDIVIDER[7:0]
Symbol
PARITYC
DESCRAMBLE
SEL_EN[1:0]
WORD_SWAP
Extension time reset registers (address 04h to 05h) bit description
Register DCSMU_PREDIV (address 06h)
LSB/MSB of polarity registers (address 08h to 09h) bit description
Register LD_CNTRL (address 0Ah)
Register
RST_EXT_LCLK
RST_EXT_DCLK 7 to 0
Register
LD_POL_LSB
LD_POL_MSB
Bit
7 to 0
7 to 0
Bit
7 to 0
Symbol
LD_POL[7:0]
LD_POL[15:8]
Access
R/W
Access
R/W
R/W
R/W
R/W
Symbol
RST_EXT_LCLK_
TIME[7:0]
RST_EXT_DCLK_
TIME[7:0]
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Value
-
Value
0
1
0
1
00
01
10
11
0
1
Access Value
R/W
-
-
Access Value
R/W
R/W
Description
predivider value for the DCMSU, expressed in LVDS
clock period
Description
parity check
Descramble control
LDVS data enable
reverse order for LVDS path
8 bits for the predivider value
disable
enable
disable descrambling
enable descrambling
LVDS data enable = align signal from channel A
LVDS data enable = align signal from channel B
LVDS data enable = 0
LVDS data enable = 1
normal operation
MSB to LSB order reversed
-
-
toggles polarity of corresponding bit
Description
specifies extension time reset,
expressed in LVDS clock periods
specify extension time reset,
expressed in DCLK periods
Description
pair within LD[7:0]
DAC1617D1G0
most significant 6 bits for the
polarity toggle
most significant 6 bits for the
polarity toggle
8 bits for the extension time reset
8 bits for the extension time reset
© IDT 2012. All rights reserved.
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