DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 22

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
10.8 Timing
The DAC1617D1G0 can operate at an update rate (f
data rate (f
The sampling position of the LVDS data can be tuned using a 16-step compensation delay
clock. An internal clock is generated to define the exact sampling position of the LVDS
data (see Figure 14, signals LDCLKPcp and LDCLKNcp) which depends on the
compensation delay.
Figure 14 shows how the compensation delay helps to recover the LVDS DDR data on
both the A and B paths.
Fig 12. DAC core clock: CML configuration with AC-coupling
Fig 13. DAC core clock: PECL configuration with AC-coupling
data
) of up to 370 MHz.
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
s
) of up to 1 Gsps and with an input
DAC1617D1G0
© IDT 2012. All rights reserved.
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