DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 25

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 11.
[1]
[2]
[3]
[4]
[5]
[6]
Table 12.
[1]
[2]
[3]
[4]
[5]
[6]
DAC1617D1G0 3
Preliminary data sheet
LVDS DDR
LVDS DDR
rate (MHz)
rate (MHz)
Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61).
Bits INTERPOLATION[1:0] of register TXCFG (see Table 23).
If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23).
Pins CLKP and CLKN (see Figure 2).
Bit PLL_PD of register PLLCFG (see Table 24).
Bits PLL_DIV[1:0] of register PLLCFG (see Table 24).
Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61).
Bits INTERPOLATION[1:0] of register TXCFG (see Table 23).
If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23).
Pins CLKP and CLKN (see Figure 2).
Bit PLL_PD of register PLLCFG (see Table 24).
Bits PLL_DIV[1:0] of register PLLCFG (see Table 24).
320
320
250
250
CDI mode 0: operating modes examples
CDI mode 1: operating modes examples
10.9.1 CDI mode 0 (x2 interpolation)
10.9.2 CDI mode 1 (x4 interpolation)
(Msps)
(Msps)
Q rate
Q rate
I rate;
I rate;
320
320
250
250
CDI mode 0 (2 interpolation) is required when the value of the LVDS DDR clock is twice
the internal maximum CDI frequency. Table 11 shows examples of applications using an
internal PLL or an external clock for the DAC core.
CDI mode 1 (4 interpolation) is required when the values of the LVDS DDR clock and the
internal CDI frequency are equal. Table 12 shows examples of applications using an
internal PLL or an external clock for the DAC core.
mode
mode
CDI
CDI
0
0
1
1
[1]
[1]
FIR mode
FIR mode
2
2
4
4
Rev. 03 — 2 July 2012
[2]
[2]
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
(Msps)
(Msps)
SSBM
SSBM
rate
rate
1000
1000
640
640
[3]
[3]
DAC rate
DAC rate
(Msps)
(Msps)
1000
1000
640
640
DAC input
DAC input
clock
clock
(MHz)
(MHz)
1000
320
640
250
DAC1617D1G0
[4]
[4]
PLL configuration
PLL configuration
status
disabled
status
disabled
enabled
enabled
PLL
PLL
[5]
[5]
© IDT 2012. All rights reserved.
divider
divider
PLL
PLL
n.a.
n.a.
2
4
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[6]
[6]