DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 48

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Table 21.
Address
0
1
2
4
5
6
7
8
9
10 0Ah
11
12 0Ch
13 0Dh
14 0Eh
15 0Fh
00h
01h
02h
04h
05h
06h
07h
08h
09h
0Bh
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Page_00 register allocation map
Register name
PH_CORR_CTL1
DAC_A_DGAIN_LSB
DAC_B_DGAIN_MSB
DAC_OUT_CTRL
COMMON
TXCFG
PLLCFG
FREQNCO_B0
FREQNCO_B1
FREQNCO_B2
FREQNCO_B3
FREQNCO_B4
PH_CORR_CTL0
DAC_A_DGAIN_MSB
DAC_B_DGAIN_LSB
10.22.3 Page 0 register allocation map
Table 21 shows an overview of all registers on page 0 (00h in hexadecimal).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NCO_ON
PH_COR
3W_SPI
PLL_BP
_ENA
Bit 7
-
-
-
PLL_BUF
SPI_RST
NCO_LP
_SEL
Bit 6
_PD
-
-
-
-
PLL_PLL
INV_SIN
_SEL
Bit 5
_PD
-
-
-
-
-
Bit 4
DAC_A_DGAIN[7:0]
DAC_B_DGAIN[7:0]
FREQ_NCO[23:16]
FREQ_NCO[31:24]
FREQ_NCO[39:32]
PHASE_COR[7:0]
FREQ_NCO[15:8]
-
-
-
-
FREQ_NCO[7:0]
PLL_DIV[1:0]
Bit definition
A_DGAIN_E
MODULATION[2:0]
Bit 3
-
PHASE_COR[12:8]
B_DGAIN_E
DAC_A_DGAIN[11:8]
DAC_B_DGAIN[11:8]
CODING
PLL_PHASE[1:0]
Bit 2
INTERPOLATION[1:0] 0000
IC_PON
MINUS
_3DB
Bit 1
GAP_PON 1000
CLIPPING
OSC_PD
_ENA
PLL_
Bit 0
Default
Bin
0111
0001
1010
0001
0110
0110
0110
0110
0110
0110
0010
0110
0010
0110
0000
0000
0000
0000
1101
0100
0000
1011
1101
0100
0000
0010
0000
0000
Hex
87h
01h
A1h
66h
66h
66h
66h
26h
00h
00h
50h
0Bh
50h
0Bh
00h