MC68HC05P1ADW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P1ADW Datasheet - Page 38

• Manufacturer Part Number: MC68HC05P1ADW
• Description: General Release Specification
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Interrupts
General Release Specification
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked by the I bit
being clear in the condition code register (CCR) and the corresponding
interrupt enable bit being set, the processor proceeds with interrupt
processing. Otherwise, the next instruction is fetched and executed. The
SWI is executed the same as any other instruction, regardless of the
state of the I bit.
When an interrupt is processed, the CPU puts the register contents on
the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$1FF0–$1FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location, shown in
Table
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the CPU state to be
recovered from the stack and normal processing to resume at the next
instruction that was executed when the interrupt took place.
shows the event sequence that occurs during interrupt processing.
Register
Freescale Semiconductor, Inc.
TSR
TSR
TSR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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4-1, will be serviced first.
Table 4-1. Vector Addresses for Interrupts and Reset
Name
Flag
OCF
TOF
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N/A
N/A
N/A
N/A
N/A
N/A
N/A
ICF
Enable
Interrupts
OCIE
TOIE
ICIE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Bit
External Interrupt
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer Overflow
Timer Output
Timer Input
Interrupt
Compare
Software
Capture
Reset
Interrupt
RESET
TIMER
TIMER
TIMER
MC68HC05P1A
CPU
SWI
IRQ
N/A
N/A
N/A
N/A
$1FFC–$1FFD
$1FFE–$1FFF
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6-$1FF7
$1FF4-$1FF5
$1FF2-$1FF3
$1FF0-$1FF1
Address
Figure 4-1
Vector
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Rev. 3.0