MC68HC05P1ADW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P1ADW Datasheet - Page 46

• Manufacturer Part Number: MC68HC05P1ADW
• Description: General Release Specification
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Resets
5.3 External Reset (RESET)
5.4 Internal Resets
5.4.1 Power-On Reset (POR)
5.4.2 Computer Operating Properly (COP) Reset
General Release Specification
The reset input is the only external reset and is connected to an internal
Schmitt trigger. The external reset occurs whenever the reset input is
driven below the lower threshold and remains in reset until the RESET
pin rises above the upper threshold. The upper and lower thresholds are
given in
The two internally generated resets are the initial power-on reset (POR)
function and the COP watchdog timer function.
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.
When the COP watchdog timer is enabled (by mask option), the internal
COP reset is generated automatically by a timeout of the COP watchdog
timer. This timer is implemented with an 18-stage ripple counter that
provides a timeout period of 65.5 ms when a 4-MHz oscillator is used.
The COP watchdog counter is cleared by writing a logic 0 to bit zero at
location $1FF0.
The COP watchdog timer can be disabled by mask option or by applying
2
operating voltage range (between V
timer output will be restored if the COP mask option is enabled.
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in
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V
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DD
Section 10. Electrical
to the IRQ pin. When the IRQ pin is returned to its normal
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Resets
Specifications.
SS
and V
DD
), the COP watchdog
MC68HC05P1A
Figure
5-2. Reading
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Rev. 3.0