MC68HC05P1ADW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P1ADW Datasheet - Page 41

• Manufacturer Part Number: MC68HC05P1ADW
• Description: General Release Specification
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC05P1A
PA0 IRQ INHIBIT
PA7 IRQ INHIBIT
(MASK OPTION)
(MASK OPTION)
MASK OPTION
IRQ PIN
(IRQ LEVEL)
DDRA0
DDRA7
NOTE:
—
PA0
PA7
IRQ VECTOR FETCH
Rev. 3.0
When the edge- and level-sensitive mask option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed to avoid the
processor re-entering the IRQ service routine.
The IRQ pin is one source of an IRQ interrupt, and a mask option can
also enable the port A pins (PA0–PA7) to act as other IRQ interrupt
sources. These sources are all combined into a single ORing function to
be latched by the IRQ latch.
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge
of the IRQ pin or a port A pin if port A interrupts have been enabled. If
edge-only sensitivity is chosen by a mask option, only the IRQ latch
output can activate a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
RST
1. Falling edge on the IRQ pin with all enabled port A interrupt pins
2. Falling edge on any enabled port A interrupt pin with all other
Figure 4-2. IRQ Function Block Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
at a high level.
enabled port A interrupt pins and the IRQ pin at a high level.
Go to: www.freescale.com
Interrupts
V
DD
LATCH
IRQ
R
General Release Specification
Hardware Interrupts
TO BIH & BIL
INSTRUCTION
SENSING
TO IRQ
PROCESSING
IN CPU
Interrupts