MC68HC05P1ADW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P1ADW Datasheet - Page 73

• Manufacturer Part Number: MC68HC05P1ADW
• Description: General Release Specification
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.6 Timer Control Register
MC68HC05P1A
—
Rev. 3.0
The timer control (TCR) and free-running counter (TMRH, TMRL,
ACRH, and ACRL) registers are the only registers of the 16-bit timer
affected by reset. The output compare port (TCMP) is forced low after
reset and remains low until OLVL is set and a valid output compare
occurs.
ICIE — Input Capture Interrupt Enable
OCIE — Output Compare Interrupt Enable
TOIE — Timer Overflow Interrupt Enable
IEDG — Input Capture Edge Select
OLVL — Output Compare Output Level Select
Reset:
$0012
Read:
Write:
Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.
Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.
Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.
Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge;
setting it selects the rising edge.
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
Freescale Semiconductor, Inc.
For More Information On This Product,
U = Unaffected
Bit 7
ICIE
0
Figure 8-11. Timer Control Register (TCR)
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OCIE
6
0
16-Bit Timer
TOIE
5
0
4
0
0
3
0
0
General Release Specification
2
0
0
Timer Control Register
IEDG
U
1
16-Bit Timer
OLVL
Bit 0
0