MC68HC05P1ADW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P1ADW Datasheet - Page 75

• Manufacturer Part Number: MC68HC05P1ADW
• Description: General Release Specification
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.8 Timer Operation During Wait Mode
8.9 Timer Operation During Stop Mode
MC68HC05P1A
—
Rev. 3.0
OCF — Output Compare Flag
TOF — Timer Overflow Flag
During wait mode, the 16-bit timer continues to operate normally and
may generate an interrupt to trigger the MCU out of wait mode.
When the MCU enters stop mode, the free-running counter stops
counting (the PH2 clock is stopped). It remains at that particular count
value until stop mode is exited by applying a low signal to the IRQ pin,
at which time the counter resumes from its stopped value as if nothing
had happened. If stop mode is exited via an external RESET (logic low
applied to the RESET pin), the counter is forced to $FFFC.
If a valid input capture edge occurs at the TCAP pin during stop mode,
the input capture detect circuitry will be armed. This action does not set
any flags or wake up the MCU, but when the MCU does wake up, there
will be an active input capture flag (and data) from the first valid edge. If
stop mode is exited by an external reset, no input capture flag or data
will be present even if a valid input capture edge was detected during
stop mode.
Bit 6 is set when the contents of the output compare registers match
the contents of the free-running counter. This flag and the output
compare interrupt can be cleared by reading register TSR followed by
writing the LSB of the output compare register pair (OCRL).
Bit 5 is set by a rollover of the free-running counter from $FFFF to
$0000. This flag and the timer overflow interrupt can be cleared by
reading register TSR followed by reading the LSB of the timer register
pair (TMRL).
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16-Bit Timer
Timer Operation During Wait Mode
General Release Specification
16-Bit Timer