MC68HC05P1ADW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P1ADW Datasheet - Page 69

• Manufacturer Part Number: MC68HC05P1ADW
• Description: General Release Specification
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC05P1A
—
Rev. 3.0
After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the LSB (OCRL)
is written. Both bytes must be written if the MSB is written. A write made
only to the LSB will not inhibit the compare function. The free-running
counter increments every four PH2 clock cycles. The minimum time
required to update the output compare registers is a function of software
rather than hardware.
The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. This procedure is recommended:
This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in
timing diagram is shown in
1. Block interrupts by setting the I bit in the condition code register
2. Write the MSB of the output compare register pair (OCRH) to
3. Read the timer status register (TSR) to arm the output compare
4. Write the LSB of the output compare register pair (OCRL) to
5. Unblock interrupts by clearing the I bit in the CCR.
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(CCR).
inhibit further compares until the LSB is written.
flag (OCF).
enable the output compare function and to clear its flag (and
interrupt).
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16-Bit Timer
Figure
8-8.
Figure 8-7
General Release Specification
and a state
Output Compare
16-Bit Timer