PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 138

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1230/1330
FIGURE 13-23:
13.11.3
The PWMPIN Configuration bit determines the PWM
output pins to be PWM output pins, or digital I/O pins,
after the device comes out of Reset. If the PWMPIN
Configuration bit is unprogrammed (default), the
PWMEN2:PWMEN0 control bits will be cleared on a
device Reset. Consequently, all PWM outputs will be
tri-stated and controlled by the corresponding PORT
and TRIS registers. If the PWMPIN Configuration bit is
programmed low, the PWMEN2:PWMEN0 control bits
will be set to ‘100’ on a device Reset:
All PWM pins will be enabled for PWM output and will
have the output polarity defined by the HPOL and
LPOL Configuration bits.
13.12 PWM Fault Input
There is one Fault input associated with the PWM
module. The main purpose of the input Fault pin is to
disable the PWM output signals and drive them into an
inactive state. The action of the Fault input is performed
DS39758B-page 136
Note:
PWM OUTPUT PIN RESET STATES
PWM Signal from Module
PWM Pin Enable
Data Bus
WR PORT
WR TRIS
RD TRIS
RD PORT
I/O pin has protection diodes to V
PWM I/O PIN BLOCK DIAGRAM
Data Latch
TRIS Latch
D
D
CK
CK
Advance Information
Q
Q
Q
Q
DD
and V
SS
. PWM polarity selection logic not shown for clarity.
1
0
directly in hardware so that when a Fault occurs, it can
be managed quickly and the PWMs outputs are put into
an inactive state to save the power devices connected
to the PWMs.
The PWM Fault input is FLTA, which can come from
I/O pins, the CPU or another module. The FLTA pin is
an active-low input so it is easy to “OR” many sources
to the same input.
The FLTCONFIG register (Register 13-8) defines the
settings of the FLTA input.
13.12.1
By setting the bit FLTAEN in the FLTCONFIG register,
the corresponding Fault input is enabled. If FLTAEN bit
is cleared, then the Fault input has no effect on the
PWM module.
Q
Note:
EN
D
The inactive state of the PWM pins is
dependent on the HPOL and LPOL Con-
figuration bit settings, which define the
active and inactive state for PWM outputs.
FAULT PIN ENABLE BIT
V
V
P
N
DD
SS
© 2006 Microchip Technology Inc.
TTL or
Schmitt
Trigger
I/O pin