PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 58

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1230/1330
TABLE 5-2:
DS39758B-page 56
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
BAUDCON
CVRCON
CMCON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
PTCON0
PTCON1
Legend:
Note 1:
File Name
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and
reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See
Section 2.6.4 “PLL in INTOSC Modes”.
The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads
as ‘0’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
A/D Result Register High Byte
A/D Result Register Low Byte
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
TMR0ON
ABDOVF
SEVTEN
PTOPS3
OSCFIP
OSCFIE
INTSRC
OSCFIF
CVREN
C2OUT
EEPGD
IDLEN
CSRC
ADFM
SPEN
RD16
PTEN
Bit 7
IPEN
—
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)
SBOREN
PLLEN
T016BIT
PTOPS2
T1RUN
C1OUT
RCIDL
PTDIR
IRCF2
CFGS
ADIP
ADIE
Bit 6
ADIF
RX9
TX9
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(1)
T1CKPS1
PTOPS1
ACQT2
C0OUT
IRVST
IRCF1
CVRR
SREN
TXEN
T0CS
RCIP
RCIF
RCIE
Bit 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Advance Information
T1CKPS0
PTOPS0
CVRSS
LVDEN
VCFG0
ACQT1
IRCF0
SCKP
SYNC
CREN
FREE
TUN4
T0SE
Bit 4
PTIP
PTIE
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
PTIF
—
RI
—
—
—
N
T1OSCEN
PTCKPS1
WRERR
CMP2IP
CMP2IE
CMP2IF
SENDB
ADDEN
PCFG3
ACQT0
BRG16
LVDL3
OSTS
CHS1
CVR3
TUN3
Bit 3
PSA
OV
TO
—
—
—
—
—
—
—
—
—
PTCKPS0
T1SYNC
CMP1IP
CMP1IF
CMP1IE
CMEN2
PCFG2
ADCS2
T0PS2
LVDL2
WREN
BRGH
LVDIP
LVDIE
CHS0
CVR2
FERR
LVDIF
TUN2
IOFS
Bit 2
PD
—
—
—
—
—
—
Z
GO/DONE
TMR1CS
PTMOD1
CMP0IP
CMP0IF
CMP0IE
CMEN1
PCFG1
ADCS1
T0PS1
LVDL1
OERR
CVR1
TRMT
SCS1
TUN1
WUE
Bit 1
POR
WR
DC
—
—
—
—
—
—
—
—
© 2006 Microchip Technology Inc.
SWDTEN
TMR1ON
PTMOD0
TMR1IP
TMR1IE
CMEN0
TMR1IF
PCFG0
ADCS0
ABDEN
T0PS0
LVDL0
ADON
SCS0
CVR0
RX9D
TUN0
TX9D
Bit 0
BOR
RD
—
—
—
—
—
—
—
C
(7)
---x xxxx 42, 58
0000 0000 42, 103
xxxx xxxx 42, 103
1111 1111 42, 101
0100 q000 42, 22
--00 0101 42, 179
---- ---0 42, 195
0q-1 11q0 42, 34
xxxx xxxx 42, 109
xxxx xxxx 42, 109
0000 0000 42, 105
xxxx xxxx 42, 172
xxxx xxxx 42, 172
0--- 0000 42, 163
---0 1111 42, 164
0-00 0000 42, 165
01-0 0-00 42, 144
0-00 0000 42, 177
000- -000 42, 173
0000 0000 42, 146
0000 0000 42, 146
0000 0000 42, 153
0000 0000 42, 151
0000 0010 42, 142
0000 000x 42, 143
0000 0000 43, 75
0000 0000 43, 75
0000 0000 43, 66
xx-0 x000 42, 67
---1 ---- 43, 97
---0 ---- 43, 93
---0 ---- 43, 95
1--1 -1-- 43, 97
0--0 -0-- 43, 93
0--0 -0-- 43, 95
-111 1111 43, 96
-000 0000 43, 92
-000 0000 43, 94
00-0 0000 43, 19
0000 0000 43, 116
00-- ---- 43, 116
POR, BOR
Value on
Details
page:
on