PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 156

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1230/1330
FIGURE 14-7:
TABLE 14-6:
14.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be
performed. The auto-wake-up feature allows the
controller to wake-up due to activity on the RX/DT line
while the EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)
DS39758B-page 154
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Name
Note:
Rcv Buffer Reg
(Interrupt Flag)
Rcv Shift Reg
Buffer Reg
Read Rcv
OERR bit
RX (pin)
RCREG
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing
the OERR (Overrun) bit to be set.
AUTO-WAKE-UP ON SYNC
BREAK CHARACTER
CREN
RCIF
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
SPEN
CSRC
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
—
—
—
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
Advance Information
bit 7/8
Stop
INT0IE
CREN
SYNC
bit
SCKP
TXIE
TXIP
Bit 4
TXIF
Word 1
RCREG
Start
bit
CMP2IF
CMP2IE
CMP2IP
bit 0
ADDEN
SENDB
BRG16
Following a wake-up event, the module generates an
RCIF
synchronously to the Q clocks in normal operating
modes (Figure 14-8) and asynchronously if the device
is in Sleep mode (Figure 14-9). The interrupt condition
is cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
RBIE
Bit 3
interrupt.
CMP1IE
CMP1IP
TMR0IF
CMP1IF
bit 7/8
BRGH
Word 2
RCREG
FERR
Bit 2
—
Stop
bit
The
CMP0IF
CMP0IE
CMP0IP
INT0IF
OERR
TRMT
Start
© 2006 Microchip Technology Inc.
WUE
Bit 1
bit
interrupt
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
bit 7/8
RBIF
Bit 0
is
Stop
bit
generated
on page
Values
Reset
41
43
43
43
42
42
42
42
42
42